1. Field of the Invention
The present invention relates to a technique for protecting a semiconductor device from electrostatic discharge.
2. Description of Related Art
In semiconductor devices, an ESD (Electrostatic Discharge) protection circuit for protecting circuits from ESD is mounted. The ESD protection circuit is provided with a trigger circuit and a discharge circuit. The trigger circuit generates a trigger signal in response to a surge voltage to supply it to the discharge circuit. The discharge circuit conducts a current from a power source line to a ground line in response to the trigger signal so as to protect a protection target circuit from being applied with an overcurrent and an overvoltage.
The ESD protection circuit is generally provided with a plurality of discharge circuits. The plurality of discharge circuits is arranged in various portions of a semiconductor device. The discharge circuits have their own delay times that are different from one another due to parasitic resistances thereof. The timing for discharge by each of the plurality of discharge circuits is shifted due to differences in the delay time, which may influence performance of the ESD protection circuit. In such a case, a buffer circuit can be provided in each of the discharge circuits to reduce the differences in the delay time.
U.S. Pat. No. 6,385,021 is an example of the ESD protection circuit which is referred to as Patent Document 1.